1. Field of the Invention
The present invention generally relates to a digital frequency synthesis technique, in particular, to a digital frequency synthesis technique for increasing fine resolution.
2. Description of Related Art
Digital frequency synthesis technique has been advancing quickly along with the increasing requirement to the quality of digital products. Accordingly, various frequency synthesis techniques have been developed regarding digital frequency resolution. For example, FIG. 1(a) is a block diagram of a conventional frequency synthesizer 10. The conventional frequency synthesizer 10 includes an accumulator 12, a read-only memory (ROM) 14, a digital-to-analog converter (DAC) 16, and a low pass filter 18. The method for the frequency synthesizer 10 to generate a synthetic signal OUT1 will be described herein. The accumulator 12 receives an accumulated value K and a clock signal CLK having a system frequency and outputs a phase angle information which varies along time to the ROM 14. The ROM 14 then generates a sine wave signal corresponding to the phase angle information according to a cosine table stored therein and outputs the sine wave signal to the DAC 16. The DAC 16 converts the sine wave signal into an analog signal and outputs the analog signal to the low pass filter 18. The low pass filter 18 filters out the part of the analog signal which does not belong to the system frequency to obtain the synthetic signal OUT1 having a synthesis frequency f0. Taking an N-bit accumulator as an example, if every time the accumulated value K is accumulated and the clock signal CLK having the system frequency is used, the output frequency f0=CLK×K/(2^N).
FIG. 1(b) is a block diagram of another conventional digital frequency synthesizer 20. The digital frequency synthesizer 20 includes an accumulator 22, a phase selection circuit 24, and a multiple phase generator 26. The accumulator 22 outputs a signal 23 having multiple bits, wherein the bits of the signal 23 are divided into most significant bits (MSBs) and least significant bits (LSBs). The phase selection circuit 24 receives the signal 23 and decodes the LSBs of the signal 23 (i.e. the remainder) by using the positive arrival time of the MSBs of the signal 23. In addition, the phase selection circuit 24 selects a phase signal among a plurality of phase signals output by the multiple phase generator 26 according to the decoding result. The MSB positive time is tuned at the positive arrival time of the MSBs of the signal 23 and the tuned signal FOUT2 is output as a synthetic signal.
It should be noted that the frequency synthesis method illustrated in FIG. 1(a) is more complicated than the method illustrated in FIG. 1(b), and fine resolution phase control is more difficult in the method in FIG. 1(a) than that in the method in FIG. 1(b). Even though the cost of the ROM 14 is eliminated in the frequency synthesis method illustrated in FIG. 1(b), the resolution of the synthetic signal cannot be improved easily. Thereby, if the fine phase resolution can be increased in a simple and flexible way, the quality of a digital frequency synthetic signal can be greatly improved.